1. Field of the Invention
The present invention relates to a semiconductor device that can improve avalanche capacity without generating breakdown voltage lowering or ON resistance increasing, and a method for manufacturing the same.
2. Background Art
In order to realize the demands of markets, such as energy saving and device downsizing, the low loss of the transient state in the ON state and switching in semiconductor devices such as MOSFET and IGBT is demanded. Here, if only the ON state is observed, low loss can be enabled by making the wafer specification in the epitaxial layer which is a bulk portion have low resistance to lower the ON resistance. However, the ON resistance and the breakdown voltage are in the trade-off relation, and by simply making the wafer specification have a low resistance, the breakdown voltage of the element is lowered, and the object cannot be achieved. Therefore, by obtaining the effect of ON-resistance reduction by the low resistivity in the wafer specifications while optimizing the cell design in the low resistant wafer specification and obtaining high breakdown voltage, the improvement of tradeoff is enhanced.
When the avalanche operation due to the turn-off serge by inductive load switching occurs with the improvement of the breakdown voltage by the optimization of cell designing, the current easily flows into the portions other than the cells. In order to obtain a high withstand even under such conditions, there has been proposed what the P-type base layer under the gate pad is formed deeper than the P-type base layer of the edge terminating portion (the circumference of the chip); or what the P-type base layer under the gate pad is made floating (for example, refer to Japanese Patent Laid-Open No. 2011-97116).